This is a classic example of a novice doing system engineering and the results of that inexperience becoming an issue. Depending on the size and financials of the company you work for this could end up costing everyone their jobs. This should be addressed before you get that far.like a design change right now, because the problem is just going to be even worse (and more expensive) later. Once this is done, you're still going to be in a world of hurt once you try to do anything on the backend and have to do any kind of timing on the design after layout. The second domain use the 'pllclk' (60MHz) that generated by PLL module from source of 100MHz external oscillator. The first domain use the 'sysclk' from 10MHz external oscillator.2. Not entirely sure the tools you use will even allow you to do this kind of hack. Hello, In my project, I have two different clock domains: 1. Once all that is done use a wrapper file around your top level file that just takes a single pin and splits it into the two clocks. Do everything based on having two clocks i.e. Then do what I've already said, make two clock ports on anything that has this seriously flawed design and make them separate clocks everywhere, then output both clocks on a top level file. ![]() How do I stop the 350MHz clock definition from propagating to the 80MHz domain? Second, the ASYNCREG property can be set in your RTL code, rather than doing it in your XDC. Take a look at this posting on (and look at the forum post linked there as well). It is required to ignore messages with any other domain number. A PTP instance is configured to work in one, and only one, domain. Every PTP message contains a domain number. These are some of the primary trait of entities. The next installment in what’s in the revision of IEEE 1588 discusses PTP domains. The 350MHz constraint is still propogating everywhere. This means that even if there are proper clock domain crossing circuits in the AXI interconnect with proper constraints, you have just removed the constraints. Different domain iclock how to Different domain iclock code what conditions dictate when it can do that thing.When we want to express what a particular model: First place to put business logic (if it makes sense)ntities should be the first place that we think of to put domain logic. I also tried putting a create_generated_clock with -divide_by 4 on common clock fanout point of the 80MHz domain. ![]() But the tool (Genus) still tells there are multiple clock waveforms driving the blue registers (both set). ![]() I defined two clocks on the same pin with create_clock, made them physically_exclusive with set_clock_groups and set_false_path between the 350MHz clock and the blue set. If I use create_clock on clk port with frequency of 350MHz, the blue set of registers including the large part of clock tree that will never be operated at more than 80MHz gets unnecessarily optimized. Blue set of registers are operated at 80MHz. The set of red registers are few in number with not much logic between them and are operated at 320MHz. They are operated at different times and there is no path between them. Here is a simplified version of my problem.
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